Phase-locked loops are often designed using LC-oscillators, which have a certain fundamental frequency. The LC-oscillator is a resonant frequency circuit comprising an inductor, which is the origin of the “L” term, and a capacitor, which is the origin of the “C” term. In a quadrature phase-locked loop (PLL) circuit, two separate inductors are positioned close to each other, where the first inductor provides in-phase oscillation whereas the second inductor provides quadrature oscillation. Together, these two inductors and their corresponding capacitors provide 4 phases of a clock, CLK0, CLK90, CLK180, and CLK270, where CLK0 and CLK180 are the in-phase oscillation signals and CLK90 and CLK270 are the quadrature oscillation signals. The first and second inductors are positioned close enough to each other such that they are self-coupled.
These circuit elements are often placed on a single substrate with other circuit elements such that they can be integrated within a single chip. There may be multiple such phase-locked loop circuits or macros provided within a certain chip design. It is important for the phase-locked loop circuits to provide steady clock signals with minimum jitter.